(a) Field of the Invention
The present invention relates to a phase shift circuit and, more particularly, to a 90.degree. phase shift circuit for use in quadrature modulation/demodulation in communication systems.
(b) Description of the Related Art
A phase shift circuit for generating a pair of carrier waves having a 90.degree. phase difference therebetween is generally used in a quadrature modulator/demodulator in communication systems. An example of the phase shift circuits is described in JP-A-5-110369. Referring to FIG. 1 showing the described phase shift circuit, the phase shift circuit comprises an CR-RC phase shifter PS1 for receiving an input signal through an input terminal 15 to deliver a pair of output signals 11 and 12 having a 90.degree. phase difference therebetween, first and second amplitude equalizers EQ18 and EQ19 for clipping the amplitudes of the pair of signals 11 and 12, respectively, to deliver amplitude-equalized signals 181 and 191, a first subtracter SU4 and first adder AD5 for receiving output signals 181 and 191 from the amplitude equalizers EQ18 and EQ19 to deliver a first difference signal 41 and a first sum signal 51, respectively, third and fourth amplitude equalizers EQ20 and EQ21 for clipping the amplitudes of the first difference signal 41 and the first sum signal 51, respectively, to output amplitude-equalized signals 201 and 211, respectively, a second subtracter SU9 and a second adder AD10 for receiving amplitude-equalized signals 201 and 211, respectively, to deliver a second difference signal 91 through output terminal 16 and a second sum signal 101 through output terminal 17, respectively. The output signals 91 and 101 have a 90.degree. phase difference and an equal amplitude, whereby the output signals 91 and 101 are generally used as a pair of carrier waves in a quadrature modulator/demodulator in a communication system.
In the phase shift circuit of FIG. 1, amplitude-equalized signals 181 and 191 delivered from the amplitude equalizers EQ18 and EQ19 can be generally represented by 2cos(.omega.t+.DELTA..PHI.) and 2cos(.omega.t-.DELTA..PHI.), respectively, with the phase difference therebetween being 2.DELTA..PHI.. Thus, sum signal (S.sub.51) 51 and difference signal (D.sub.41) 41 output from the first adder AD5 and the first subtracter SU4 are expressed by: ##EQU1##
Comparing expressions (1) and (2), it is understood that the phase difference between the difference signal 41 from the subtracter 4 and the sum signal 51 from the adder 5 is exactly 90.degree., and that the ratio between both the amplitudes is expressed by: EQU sin(.DELTA..PHI.)/cos(.DELTA..PHI.)=tan(.DELTA..PHI.) (3).
From the above description, it will be understood that the first subtracter SU4 and the first adder AD5 substantially act as phase/amplitude converters, the outputs of which have a phase difference of 90.degree. therebetween. Thus, after the difference signal 41 and the sum signal 51 are subjected to amplitude equalization by the amplitude equalizers EQ20 and EQ21 and further subtraction and addition by the second subtracter SU9 and the second adder AD10, respectively, a pair of carrier signals 91 and 101 can be obtained theoretically having an exact phase difference of 90.degree. therebetween and an equal amplitude.
However, in the conventional phase shift circuit as described above, if the signal lines transmitting the signals 181, 191, 201 and 211 from the amplitude equalizers EQ18, EQ19, EQ20 and EQ21 have significant parasitic capacitances and parasitic resistances, the outputs of each pair of amplitude equalizers have a phase error therebetween. The phase error cannot be eliminated even after iterated combinations of addition/subtraction and amplitude equalization.
Especially, in the case of a high frequency input signal, the parasitic capacitance and the parasitic resistance have more significant influences upon the output signals and thereby degrade the modulation and/or demodulation in communications systems using the carrier signals output from the conventional phase shift circuit.